//------------------------------------------------------------------------------
// File                     : ahb_sram.v
// Author                   : TG
// Key Words                :
// Modification History     :
//      Date        By        Version        Change Description
//      2021-12-05  TG        1.0            original
//
// Editor                   : VSCode, Tab Size(4)
// Description              : Top Module of AHB SRAM Controller.
//
//------------------------------------------------------------------------------
`timescale 1ns / 1ps

module ahb_sram #( 
    parameter                       SYNC_RESET = 1,
    parameter                       AHB_DWIDTH = 32,
    parameter                       AHB_AWIDTH = 32,
    parameter 		            SIZE_IN_BYTES = 2048,
    parameter                       ADD_WIDTH = $clog2(SIZE_IN_BYTES)   
)
(
    //----------------------------------
    // IO Declarations
    //----------------------------------
    // Inputs
    input                           HCLK,
    input                           HRESETN,
    input                           HSEL,
    input                           HREADYIN,
    input [1:0]                     HTRANS,
    input [2:0]                     HBURST,
    input [2:0]                     HSIZE,
    input [AHB_DWIDTH-1:0]          HWDATA,
    input [AHB_AWIDTH-1:0]          HADDR,
    input                           HWRITE,
    // Outputs
    output [AHB_DWIDTH-1:0]         HRDATA,
    output [1:0]                    HRESP,
    output                          HREADYOUT
);

    //----------------------------------
    // Variable Declarations
    //----------------------------------
    wire [ADD_WIDTH-1:0]            HADDR_cal;
    wire [2:0]                      ahbsram_size;
    wire [ADD_WIDTH-1:0]            ahbsram_addr;
    wire [31:0]                     ahbsram_wdata;
    wire                            ahbsram_write;
    wire [31:0]                     sramahb_rdata;
    wire                            sramahb_ack;

    //----------------------------------
    // Start of Main Code
    //----------------------------------
    assign HADDR_cal = HADDR[ADD_WIDTH-1:0];

    // Instantiations
    ahb_sram_if #(
        .AHB_DWIDTH                 (AHB_DWIDTH),
        .AHB_AWIDTH                 (AHB_AWIDTH),
        .ADD_WIDTH                  (ADD_WIDTH), 
        .SYNC_RESET                 (SYNC_RESET)
    )       
    u_ahb_sram_if (        
        .HCLK                       (HCLK),
        .HRESETN                    (HRESETN),
        .HSEL                       (HSEL),
        .HTRANS                     (HTRANS),
        .HBURST                     (HBURST),
        .HWRITE                     (HWRITE),
        .HWDATA                     (HWDATA),
        .HSIZE                      (HSIZE),
        .HADDR                      (HADDR_cal),
        .HREADYIN                   (HREADYIN),
        // From SRAM Control signals
        .sramahb_ack                (sramahb_ack),
        .sramahb_rdata              (sramahb_rdata),
        // Outputs      
        .HREADYOUT                  (HREADYOUT),
        .HRESP                      (HRESP),
        // To SRAM Control signals
        .ahbsram_req                (ahbsram_req),
        .ahbsram_write              (ahbsram_write),
        .ahbsram_wdata              (ahbsram_wdata),
        .ahbsram_size               (ahbsram_size),
        .ahbsram_addr               (ahbsram_addr),
        .HRDATA                     (HRDATA)
    );

    sram_ctrl_if #(
        .ADD_WIDTH                  (ADD_WIDTH),
        .SYNC_RESET                 (SYNC_RESET)
    )       
    u_sram_ctrl_if (     
        .HCLK                       (HCLK),
        .HRESETN                    (HRESETN),
        // From AHB Interface signals
        .ahbsram_req                (ahbsram_req),
        .ahbsram_write              (ahbsram_write),
        .ahbsram_wdata              (ahbsram_wdata),
        .ahbsram_size               (ahbsram_size),
        .ahbsram_addr               (ahbsram_addr),
        // Outputs
        // To AHB Interface signals
        .sramahb_ack                (sramahb_ack),
        .sramahb_rdata              (sramahb_rdata)
    );

endmodule
